© 2010 Microchip Technology Inc. DS70205C-page 11-13
Section 11. Timers
Timers
11
11.4.3 Synchronous Counter Mode
In Synchronous Counter mode, the input clock to the timer is derived from the external clock input
divided by a programmable prescaler. In this mode, the external clock input is synchronized with
the internal device clock. When the timer is enabled, it increments by one on every rising edge
of the input clock, and generates an interrupt on a period match.
To configure Synchronous Counter mode:
• Set the TSYNC control bit (TxCON<2>) for a Type A timer to enable clock synchronization.
For a Type B or Type C timer, the external clock input is always synchronized.
• Set the TCS control bit (TxCON<1>) to select the external clock source.
A timer operating from a synchronized external clock source does not operate in Sleep mode,
because the synchronization circuit is shut off during Sleep mode.
For Type C timers, it is necessary for the external clock input period to be high for at least 0.5 T
CY
(and an additional input buffer delay of 20 ns), and low for at least 0.5 TCY (and an additional input
buffer delay of 20 ns) for proper synchronization.
The clock synchronization for a Type A and Type B timer is performed after the prescaler and the
prescaler output changes on the rising edge of the input. Therefore, for a Type A and Type B
timer, the external clock input period must be at least 0.5 T
CY (and an additional input buffer delay
of 20 ns) divided by the prescaler value.
However, the high and low time of the external clock input must not violate the minimum
pulse-width requirement of 10 ns nominal (or 50 MHz nominal frequency).
Example 11-3 illustrates the code sequence to set up the Timer1 module in Synchronous
Counter mode. This code generates an interrupt after counting 1000 rising edges in the TxCK
pin.
Example 11-3: Initialization Code for 16-Bit Synchronous Counter Mode
Note 1: For the external clock timing requirement in Synchronous Counter mode, refer to
the “Electrical Characteristics” chapter of the specific device data sheet.
2: Timers, when configured for the External Counter mode (TCS = 1), operate as fol-
lows: Type A and Type B timers start counting from the second rising edge, while
Type C timers start counting from the first rising edge.
3: The PRx register resets on the subsequent rising edge of the timer clock input.
4: The TxIF bit is set one instruction cycle after a period match.
Note: The timer counts PRx times for the first TxIF event and (PRx + 1) times for all
subsequent TxIF events. For applications in which the asymmetry in interrupt timing
is not acceptable, it is recommended to ignore the first TxIF event after enabling the
timer.
T1CONbits.TON = 0; // Disable Timer
T1CONbits.TCS = 1; // Select external clock source
T1CONbits.TSYNC = 1; // Enable Synchronization
T1CONbits.TCKPS = 0b00; // Select 1:1 Prescaler
TMR1 = 0x00; // Clear timer register
PR1 = 999; // Load the period value
IPC0bits.T1IP = 0x01; // Set Timer1 Interrupt Priority Level
IFS0bits.T1IF = 0; // Clear Timer1 Interrupt Flag
IEC0bits.T1IE = 1; // Enable Timer1 interrupt
T1CONbits.TON = 1; // Start Timer
/* Example code for Timer1 ISR */
void __attribute__((__interrupt__, no_auto_psv)) _T1Interrupt(void)
{
/* Interrupt Service Routine code goes here */
IFS0bits.T1IF = 0; // Clear Timer1 Interrupt Flag
}
(56 Seiten)
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