dsPIC33F/PIC24H Family Reference Manual
DS70205C-page 11-10 © 2010 Microchip Technology Inc.
11.4 MODES OF OPERATION
The Timer module can operate in one of the following modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode (Type A timer only)
In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle
clock (F
CY). In Synchronous and Asynchronous Counter modes, the input clock is derived from
the external clock input at the TxCK pin.
The Timer modes are determined by the following bits:
• TCS (TxCON<1>): Timer Clock Source Control bit
• TSYNC (TxCON<2>): Timer Synchronization Control bit (Type A timer only)
• TGATE (TxCON<6>): Timer Gate Control bit
Timer control bit settings for different operating modes are provided in Table 11-1, as follows:
The input clock (F
CY or TxCK) to all 16-bit timers has prescale options of 1:1, 1:8, 1:64 and 1:256.
The clock prescaler is selected using the Timer Clock Prescaler bits (TCKPS) in the Timer
Control register (TxCON<5:4>). The prescaler counter is cleared when any of the following
occurs:
• A write to the Timer register (TMRx) or Timer Control register (TxCON)
• Clearing the Timer Enable bit (TON) in the Timer Control register (TxCON<15>)
• Any device Reset
The Timer module is enabled or disabled using the TON bit (TxCON<15>).
11.4.1 Timer Mode
In Timer mode, the input clock to the timer is derived from the internal clock (FCY), divided by a
programmable prescaler. When the timer is enabled, it increments by one on every rising edge
of the input clock and generates an interrupt on a period match. Figure 11-4 illustrates the timer
operation.
To configure Timer mode:
• Clear the TCS control bit (TxCON<1>) to select the internal clock source
• Clear the TGATE control bit (TxCON<6>) to disable Gated Timer mode operation
Setting the TSYNC bit (TxCON<2>) has no effect since the internal clock is always synchronized.
Example 11-1 illustrates the code sequence to set up Timer1 in 16-bit Timer mode. This code
generates an interrupt on every 10 instruction cycles.
Table 11-1: Timer Modes Configuration
Mode
Bit Setting
TCS
TGATE
(2)
TSYNC
(1)
Timer 00x
Gated Timer 01x
Synchronous Counter 1x1
Asynchronous Counter
(3)
1x0
Note 1: TSYNC bit is available for Type A timer only and is ignored for both of the timer
modes.
2: TGATE bit is ignored for both the counter modes.
3: Asynchronous Counter mode is supported by Type A timer only.
Note 1: The PRx register resets one timer clock period only after the TxIF bit is set.
2: The TxIF bit is set one instruction cycle after a period match.
(56 Seiten)
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