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DS41190E-page 60 © 2007 Microchip Technology Inc.

FIGURE 9-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal RESET

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal RESET

T

PWRT

TOST

TPWRT

TOST

VDD

MCLR

Internal POR

PWRT Time-out

OST Time-out

Internal RESET

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