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© 2006 Microchip Technology Inc. DS70183A-page 16-17
Section 16. Analog-to-Digital Converter (ADC)
A
D
C
16
16.6 SELECTING THE A/D CONVERSION CLOCK
The ADC module has a maximum rate at which conversions can be completed. An analog
module clock, T
AD, controls the conversion timing. The A/D conversion requires 12 clock periods
(12 T
AD) in the 10-bit mode and 14 clock periods (14 TAD) in the 12-bit mode. The A/D conversion
clock is derived from either the device instruction clock or an internal RC clock source.
The period of the A/D conversion clock is software selected using a 6-bit counter. There are 256
possible options for T
AD, specified by the ADC Conversion Clock Select (ADCS<7:0>) bits
(ADxCON3<7:0>). Equation 16-1 gives the T
AD value as a function of the ADCS control bits and
the device instruction cycle clock period, T
CY.
Equation 16-1: A/D Conversion Clock Period
For correct A/D conversions, the A/D conversion clock (T
AD) must be selected to ensure a
minimum T
AD time of 75 nsec.
The ADC module has a dedicated internal RC clock source that can be used to perform
conversions. The internal RC clock source should be used when A/D conversions are performed
while the device is in Sleep mode. The internal RC oscillator is selected by setting the ADC Con-
version Clock Source (ADRC) bit (ADxCON3<15>). When the ADRC bit is set, the ADCS<7:0>
bits have no effect on the A/D operation.
Figure 16-4: A/D Conversion Clock Period Block Diagram
T
AD = TCY(ADCS + 1)
ADCS =
T
AD
TCY
– 1
0
1
ADC Internal
RC Clock
Clock Multiplier
1, 2, 3, 4, 5,..., 256
ADxCON3<15>
TCY
TAD
8
ADxCON3<7:0>
A/D Conversion
- HIGHLIGHTS 1
- 16.1 INTRODUCTION 2
- 16.2 CONTROL REGISTERS 4
- (1, 2, 3) 13
- AD specification 14
- 16.8 ENABLING THE MODULE 20
- 16.10 HOW TO START SAMPLING 21
- 16.11.1 Manual 22
- AD0 TAD0 23
- TSMP = SAMC<4:0>*TAD 24
- AD Based Conversion Start 25
- AD. Because automatic sample 26
- SMP = SAMC<4:0> * TAD 27
- Sampling 29
- SAMPLING/CONVERSION SEQUENCES 31
- 16.12.3 Aborting Sampling 32
- 16.12.4 Aborting a Conversion 32
- REF-) as the input to the 37
- Conversion 37
- REF- for CH0- input 38
- CONVTCONVTCONVTCONV 41
- REF- Interrupt 48
- HOLD) must 49
- HOLD. The com 49
- S, is 200Ω. After the analog 49
- 16.19 ADC ACCURACY/ERROR 54
- 16.21 CODE EXAMPLES 54
- 16.23 EFFECTS OF A RESET 62
- Table 16-10: ADC Register Map 63
- Legend: u = unknown 63
- 16.25 DESIGN TIPS 64
- 16.27 REVISION HISTORY 66
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